As computer processing power continues to increase, memory capacity becomes an issue for future computer and server performance. Memory capacity problems are exacerbated as the speed of memory increases, such as with the development of second generation double data rate dynamic random access memories (DDR2-DRAMs) and third generation double data rate dynamic random access memories (DDR3-DRAMs). With each increase in memory capacity more traces are needed to support increased clock speeds and as memory speeds increase the memory capacity that can be supported decreases due to problems such as noise and cross-talk.
To address these issues, the industry developed a memory interface capable of scaling with the increasing speeds of memory while providing a long term alternative for next generation memory solutions. This architecture has become an industry standard referred to as fully buffered dual in-line memory module (FB-DIMM). An FB-DIMM includes a bi-directional serial interface that simplifies board electrical routing and eliminates the requirement for additional memory controllers. Compared to registered DIMM technology, FB-DIMMs provide larger memory capacities, higher bandwidths, and lower pin counts.
Typically, each FB-DIMM includes an advanced memory buffer (AMB) and a selected number of dynamic random access memories (DRAMs), such as DDR2-DRAMs and DDR3-DRAMs. The AMB is responsible for handling FB-DIMM channel and memory requests to and from the local FB-DIMM and for forwarding the requests to other FB-DIMMs. The AMB receives commands, addresses and write data from a memory controller or via another AMB. The AMB transmits read data to the memory controller directly or via another FB-DIMM. Clock signals and data are recovered from the data by a clock and data recovery circuit (CDR).
The CDR recovers clock signals and data from the data and locks a clock signal to transitions in the data to accurately acquire data for use at the local FB-DIMM or transmission of the data to other FB-DIMMs. Often the phase of the clock signal is locked to the data transitions as quickly as possible. Typically, the incoming data stream is sampled with multiple clock phases to find the nearest clock phase to transitions in the data. Alternatively, the CDR includes an analog dual loop architecture, such as CDRs used in disk drive applications. Each of these methods achieves fast phase convergence at the cost of area and power consumption.
For these and other reasons there is a need for the present invention.